xen-vtx-unstable

annotate linux-2.6-xen-sparse/include/asm-xen/asm-i386/system.h @ 6776:e7c7196fa329

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author cl349@firebug.cl.cam.ac.uk
date Tue Sep 13 15:46:49 2005 +0000 (2005-09-13)
parents 4d899a738d59 dd668f7527cb
children 72e4e2aab342
rev   line source
cl349@4087 1 #ifndef __ASM_SYSTEM_H
cl349@4087 2 #define __ASM_SYSTEM_H
cl349@4087 3
cl349@4087 4 #include <linux/config.h>
cl349@4087 5 #include <linux/kernel.h>
cl349@4087 6 #include <linux/bitops.h>
kaf24@6760 7 #include <asm/synch_bitops.h>
cl349@4087 8 #include <asm/segment.h>
cl349@4087 9 #include <asm/cpufeature.h>
cl349@4087 10 #include <asm-xen/hypervisor.h>
sos22@5466 11 #include <asm/smp_alt.h>
cl349@4087 12
cl349@4087 13 #ifdef __KERNEL__
cl349@4087 14
cl349@4087 15 struct task_struct; /* one of the stranger aspects of C forward declarations.. */
cl349@4087 16 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
cl349@4087 17
cl349@4087 18 #define switch_to(prev,next,last) do { \
cl349@4087 19 unsigned long esi,edi; \
cl349@4087 20 asm volatile("pushfl\n\t" \
cl349@4087 21 "pushl %%ebp\n\t" \
cl349@4087 22 "movl %%esp,%0\n\t" /* save ESP */ \
cl349@4087 23 "movl %5,%%esp\n\t" /* restore ESP */ \
cl349@4087 24 "movl $1f,%1\n\t" /* save EIP */ \
cl349@4087 25 "pushl %6\n\t" /* restore EIP */ \
cl349@4087 26 "jmp __switch_to\n" \
cl349@4087 27 "1:\t" \
cl349@4087 28 "popl %%ebp\n\t" \
cl349@4087 29 "popfl" \
cl349@4087 30 :"=m" (prev->thread.esp),"=m" (prev->thread.eip), \
cl349@4087 31 "=a" (last),"=S" (esi),"=D" (edi) \
cl349@4087 32 :"m" (next->thread.esp),"m" (next->thread.eip), \
cl349@4087 33 "2" (prev), "d" (next)); \
cl349@4087 34 } while (0)
cl349@4087 35
cl349@4087 36 #define _set_base(addr,base) do { unsigned long __pr; \
cl349@4087 37 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
cl349@4087 38 "rorl $16,%%edx\n\t" \
cl349@4087 39 "movb %%dl,%2\n\t" \
cl349@4087 40 "movb %%dh,%3" \
cl349@4087 41 :"=&d" (__pr) \
cl349@4087 42 :"m" (*((addr)+2)), \
cl349@4087 43 "m" (*((addr)+4)), \
cl349@4087 44 "m" (*((addr)+7)), \
cl349@4087 45 "0" (base) \
cl349@4087 46 ); } while(0)
cl349@4087 47
cl349@4087 48 #define _set_limit(addr,limit) do { unsigned long __lr; \
cl349@4087 49 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
cl349@4087 50 "rorl $16,%%edx\n\t" \
cl349@4087 51 "movb %2,%%dh\n\t" \
cl349@4087 52 "andb $0xf0,%%dh\n\t" \
cl349@4087 53 "orb %%dh,%%dl\n\t" \
cl349@4087 54 "movb %%dl,%2" \
cl349@4087 55 :"=&d" (__lr) \
cl349@4087 56 :"m" (*(addr)), \
cl349@4087 57 "m" (*((addr)+6)), \
cl349@4087 58 "0" (limit) \
cl349@4087 59 ); } while(0)
cl349@4087 60
cl349@4087 61 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
cl349@4087 62 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1)>>12 )
cl349@4087 63
cl349@4087 64 static inline unsigned long _get_base(char * addr)
cl349@4087 65 {
cl349@4087 66 unsigned long __base;
cl349@4087 67 __asm__("movb %3,%%dh\n\t"
cl349@4087 68 "movb %2,%%dl\n\t"
cl349@4087 69 "shll $16,%%edx\n\t"
cl349@4087 70 "movw %1,%%dx"
cl349@4087 71 :"=&d" (__base)
cl349@4087 72 :"m" (*((addr)+2)),
cl349@4087 73 "m" (*((addr)+4)),
cl349@4087 74 "m" (*((addr)+7)));
cl349@4087 75 return __base;
cl349@4087 76 }
cl349@4087 77
cl349@4087 78 #define get_base(ldt) _get_base( ((char *)&(ldt)) )
cl349@4087 79
cl349@4087 80 /*
cl349@4087 81 * Load a segment. Fall back on loading the zero
cl349@4087 82 * segment if something goes wrong..
cl349@4087 83 */
cl349@4087 84 #define loadsegment(seg,value) \
cl349@4087 85 asm volatile("\n" \
cl349@4087 86 "1:\t" \
vh249@5730 87 "mov %0,%%" #seg "\n" \
cl349@4087 88 "2:\n" \
cl349@4087 89 ".section .fixup,\"ax\"\n" \
cl349@4087 90 "3:\t" \
cl349@4087 91 "pushl $0\n\t" \
cl349@4087 92 "popl %%" #seg "\n\t" \
cl349@4087 93 "jmp 2b\n" \
cl349@4087 94 ".previous\n" \
cl349@4087 95 ".section __ex_table,\"a\"\n\t" \
cl349@4087 96 ".align 4\n\t" \
cl349@4087 97 ".long 1b,3b\n" \
cl349@4087 98 ".previous" \
vh249@5730 99 : :"m" (value))
cl349@4087 100
cl349@4087 101 /*
cl349@4087 102 * Save a segment register away
cl349@4087 103 */
cl349@4087 104 #define savesegment(seg, value) \
vh249@5730 105 asm volatile("mov %%" #seg ",%0":"=m" (value))
cl349@4087 106
cl349@4087 107 /*
cl349@4087 108 * Clear and set 'TS' bit respectively
cl349@4087 109 */
cl349@4112 110 #define clts() (HYPERVISOR_fpu_taskswitch(0))
kaf24@5367 111 #define read_cr0() ({ \
kaf24@5367 112 unsigned int __dummy; \
kaf24@5367 113 __asm__( \
kaf24@5367 114 "movl %%cr0,%0\n\t" \
kaf24@5367 115 :"=r" (__dummy)); \
kaf24@5367 116 __dummy; \
kaf24@5367 117 })
cl349@4087 118 #define write_cr0(x) \
kaf24@5367 119 __asm__("movl %0,%%cr0": :"r" (x));
kaf24@5367 120
kaf24@5367 121 #define read_cr4() ({ \
kaf24@5367 122 unsigned int __dummy; \
kaf24@5367 123 __asm__( \
kaf24@5367 124 "movl %%cr4,%0\n\t" \
kaf24@5367 125 :"=r" (__dummy)); \
kaf24@5367 126 __dummy; \
kaf24@5367 127 })
cl349@4087 128 #define write_cr4(x) \
kaf24@5367 129 __asm__("movl %0,%%cr4": :"r" (x));
cl349@4112 130 #define stts() (HYPERVISOR_fpu_taskswitch(1))
cl349@4087 131
cl349@4087 132 #endif /* __KERNEL__ */
cl349@4087 133
cl349@4112 134 #define wbinvd() \
cl349@4112 135 __asm__ __volatile__ ("wbinvd": : :"memory");
cl349@4087 136
cl349@4087 137 static inline unsigned long get_limit(unsigned long segment)
cl349@4087 138 {
cl349@4087 139 unsigned long __limit;
cl349@4087 140 __asm__("lsll %1,%0"
cl349@4087 141 :"=r" (__limit):"r" (segment));
cl349@4087 142 return __limit+1;
cl349@4087 143 }
cl349@4087 144
cl349@4087 145 #define nop() __asm__ __volatile__ ("nop")
cl349@4087 146
cl349@4087 147 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
cl349@4087 148
cl349@4087 149 #define tas(ptr) (xchg((ptr),1))
cl349@4087 150
cl349@4087 151 struct __xchg_dummy { unsigned long a[100]; };
cl349@4087 152 #define __xg(x) ((struct __xchg_dummy *)(x))
cl349@4087 153
cl349@4087 154
cl349@4087 155 /*
cl349@4087 156 * The semantics of XCHGCMP8B are a bit strange, this is why
cl349@4087 157 * there is a loop and the loading of %%eax and %%edx has to
cl349@4087 158 * be inside. This inlines well in most cases, the cached
cl349@4087 159 * cost is around ~38 cycles. (in the future we might want
cl349@4087 160 * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
cl349@4087 161 * might have an implicit FPU-save as a cost, so it's not
cl349@4087 162 * clear which path to go.)
cl349@4087 163 *
cl349@4087 164 * cmpxchg8b must be used with the lock prefix here to allow
cl349@4087 165 * the instruction to be executed atomically, see page 3-102
cl349@4087 166 * of the instruction set reference 24319102.pdf. We need
cl349@4087 167 * the reader side to see the coherent 64bit value.
cl349@4087 168 */
cl349@4087 169 static inline void __set_64bit (unsigned long long * ptr,
cl349@4087 170 unsigned int low, unsigned int high)
cl349@4087 171 {
cl349@4087 172 __asm__ __volatile__ (
cl349@4087 173 "\n1:\t"
cl349@4087 174 "movl (%0), %%eax\n\t"
cl349@4087 175 "movl 4(%0), %%edx\n\t"
cl349@4087 176 "lock cmpxchg8b (%0)\n\t"
cl349@4087 177 "jnz 1b"
cl349@4087 178 : /* no outputs */
cl349@4087 179 : "D"(ptr),
cl349@4087 180 "b"(low),
cl349@4087 181 "c"(high)
cl349@4087 182 : "ax","dx","memory");
cl349@4087 183 }
cl349@4087 184
cl349@4087 185 static inline void __set_64bit_constant (unsigned long long *ptr,
cl349@4087 186 unsigned long long value)
cl349@4087 187 {
cl349@4087 188 __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
cl349@4087 189 }
cl349@4087 190 #define ll_low(x) *(((unsigned int*)&(x))+0)
cl349@4087 191 #define ll_high(x) *(((unsigned int*)&(x))+1)
cl349@4087 192
cl349@4087 193 static inline void __set_64bit_var (unsigned long long *ptr,
cl349@4087 194 unsigned long long value)
cl349@4087 195 {
cl349@4087 196 __set_64bit(ptr,ll_low(value), ll_high(value));
cl349@4087 197 }
cl349@4087 198
cl349@4087 199 #define set_64bit(ptr,value) \
cl349@4087 200 (__builtin_constant_p(value) ? \
cl349@4087 201 __set_64bit_constant(ptr, value) : \
cl349@4087 202 __set_64bit_var(ptr, value) )
cl349@4087 203
cl349@4087 204 #define _set_64bit(ptr,value) \
cl349@4087 205 (__builtin_constant_p(value) ? \
cl349@4087 206 __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
cl349@4087 207 __set_64bit(ptr, ll_low(value), ll_high(value)) )
cl349@4087 208
cl349@4087 209 /*
cl349@4087 210 * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
cl349@4087 211 * Note 2: xchg has side effect, so that attribute volatile is necessary,
cl349@4087 212 * but generally the primitive is invalid, *ptr is output argument. --ANK
cl349@4087 213 */
cl349@4087 214 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
cl349@4087 215 {
cl349@4087 216 switch (size) {
cl349@4087 217 case 1:
cl349@4087 218 __asm__ __volatile__("xchgb %b0,%1"
cl349@4087 219 :"=q" (x)
cl349@4087 220 :"m" (*__xg(ptr)), "0" (x)
cl349@4087 221 :"memory");
cl349@4087 222 break;
cl349@4087 223 case 2:
cl349@4087 224 __asm__ __volatile__("xchgw %w0,%1"
cl349@4087 225 :"=r" (x)
cl349@4087 226 :"m" (*__xg(ptr)), "0" (x)
cl349@4087 227 :"memory");
cl349@4087 228 break;
cl349@4087 229 case 4:
cl349@4087 230 __asm__ __volatile__("xchgl %0,%1"
cl349@4087 231 :"=r" (x)
cl349@4087 232 :"m" (*__xg(ptr)), "0" (x)
cl349@4087 233 :"memory");
cl349@4087 234 break;
cl349@4087 235 }
cl349@4087 236 return x;
cl349@4087 237 }
cl349@4087 238
cl349@4087 239 /*
cl349@4087 240 * Atomic compare and exchange. Compare OLD with MEM, if identical,
cl349@4087 241 * store NEW in MEM. Return the initial value in MEM. Success is
cl349@4087 242 * indicated by comparing RETURN with OLD.
cl349@4087 243 */
cl349@4087 244
cl349@4087 245 #ifdef CONFIG_X86_CMPXCHG
cl349@4087 246 #define __HAVE_ARCH_CMPXCHG 1
cl349@4087 247 #endif
cl349@4087 248
cl349@4087 249 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
cl349@4087 250 unsigned long new, int size)
cl349@4087 251 {
cl349@4087 252 unsigned long prev;
cl349@4087 253 switch (size) {
cl349@4087 254 case 1:
sos22@5466 255 __asm__ __volatile__(LOCK "cmpxchgb %b1,%2"
cl349@4087 256 : "=a"(prev)
cl349@4087 257 : "q"(new), "m"(*__xg(ptr)), "0"(old)
cl349@4087 258 : "memory");
cl349@4087 259 return prev;
cl349@4087 260 case 2:
sos22@5466 261 __asm__ __volatile__(LOCK "cmpxchgw %w1,%2"
cl349@4087 262 : "=a"(prev)
cl349@4087 263 : "q"(new), "m"(*__xg(ptr)), "0"(old)
cl349@4087 264 : "memory");
cl349@4087 265 return prev;
cl349@4087 266 case 4:
sos22@5466 267 __asm__ __volatile__(LOCK "cmpxchgl %1,%2"
cl349@4087 268 : "=a"(prev)
cl349@4087 269 : "q"(new), "m"(*__xg(ptr)), "0"(old)
cl349@4087 270 : "memory");
cl349@4087 271 return prev;
cl349@4087 272 }
cl349@4087 273 return old;
cl349@4087 274 }
cl349@4087 275
cl349@4087 276 #define cmpxchg(ptr,o,n)\
cl349@4087 277 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
cl349@4087 278 (unsigned long)(n),sizeof(*(ptr))))
cl349@4087 279
cl349@4087 280 #ifdef __KERNEL__
cl349@4087 281 struct alt_instr {
cl349@4087 282 __u8 *instr; /* original instruction */
cl349@4087 283 __u8 *replacement;
cl349@4087 284 __u8 cpuid; /* cpuid bit set for replacement */
cl349@4087 285 __u8 instrlen; /* length of original instruction */
cl349@4087 286 __u8 replacementlen; /* length of new instruction, <= instrlen */
cl349@4087 287 __u8 pad;
cl349@4087 288 };
cl349@4087 289 #endif
cl349@4087 290
cl349@4087 291 /*
cl349@4087 292 * Alternative instructions for different CPU types or capabilities.
cl349@4087 293 *
cl349@4087 294 * This allows to use optimized instructions even on generic binary
cl349@4087 295 * kernels.
cl349@4087 296 *
cl349@4087 297 * length of oldinstr must be longer or equal the length of newinstr
cl349@4087 298 * It can be padded with nops as needed.
cl349@4087 299 *
cl349@4087 300 * For non barrier like inlines please define new variants
cl349@4087 301 * without volatile and memory clobber.
cl349@4087 302 */
cl349@4087 303 #define alternative(oldinstr, newinstr, feature) \
cl349@4087 304 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
cl349@4087 305 ".section .altinstructions,\"a\"\n" \
cl349@4087 306 " .align 4\n" \
cl349@4087 307 " .long 661b\n" /* label */ \
cl349@4087 308 " .long 663f\n" /* new instruction */ \
cl349@4087 309 " .byte %c0\n" /* feature bit */ \
cl349@4087 310 " .byte 662b-661b\n" /* sourcelen */ \
cl349@4087 311 " .byte 664f-663f\n" /* replacementlen */ \
cl349@4087 312 ".previous\n" \
cl349@4087 313 ".section .altinstr_replacement,\"ax\"\n" \
cl349@4087 314 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
cl349@4087 315 ".previous" :: "i" (feature) : "memory")
cl349@4087 316
cl349@4087 317 /*
cl349@4087 318 * Alternative inline assembly with input.
cl349@4087 319 *
cl349@4087 320 * Pecularities:
cl349@4087 321 * No memory clobber here.
cl349@4087 322 * Argument numbers start with 1.
cl349@4087 323 * Best is to use constraints that are fixed size (like (%1) ... "r")
cl349@4087 324 * If you use variable sized constraints like "m" or "g" in the
cl349@4087 325 * replacement maake sure to pad to the worst case length.
cl349@4087 326 */
cl349@4087 327 #define alternative_input(oldinstr, newinstr, feature, input...) \
cl349@4087 328 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
cl349@4087 329 ".section .altinstructions,\"a\"\n" \
cl349@4087 330 " .align 4\n" \
cl349@4087 331 " .long 661b\n" /* label */ \
cl349@4087 332 " .long 663f\n" /* new instruction */ \
cl349@4087 333 " .byte %c0\n" /* feature bit */ \
cl349@4087 334 " .byte 662b-661b\n" /* sourcelen */ \
cl349@4087 335 " .byte 664f-663f\n" /* replacementlen */ \
cl349@4087 336 ".previous\n" \
cl349@4087 337 ".section .altinstr_replacement,\"ax\"\n" \
cl349@4087 338 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
cl349@4087 339 ".previous" :: "i" (feature), ##input)
cl349@4087 340
cl349@4087 341 /*
cl349@4087 342 * Force strict CPU ordering.
cl349@4087 343 * And yes, this is required on UP too when we're talking
cl349@4087 344 * to devices.
cl349@4087 345 *
cl349@4087 346 * For now, "wmb()" doesn't actually do anything, as all
cl349@4087 347 * Intel CPU's follow what Intel calls a *Processor Order*,
cl349@4087 348 * in which all writes are seen in the program order even
cl349@4087 349 * outside the CPU.
cl349@4087 350 *
cl349@4087 351 * I expect future Intel CPU's to have a weaker ordering,
cl349@4087 352 * but I'd also expect them to finally get their act together
cl349@4087 353 * and add some real memory barriers if so.
cl349@4087 354 *
cl349@4087 355 * Some non intel clones support out of order store. wmb() ceases to be a
cl349@4087 356 * nop for these.
cl349@4087 357 */
cl349@4087 358
cl349@4087 359
cl349@4087 360 /*
cl349@4087 361 * Actually only lfence would be needed for mb() because all stores done
cl349@4087 362 * by the kernel should be already ordered. But keep a full barrier for now.
cl349@4087 363 */
cl349@4087 364
cl349@4087 365 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
cl349@4087 366 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
cl349@4087 367
cl349@4087 368 /**
cl349@4087 369 * read_barrier_depends - Flush all pending reads that subsequents reads
cl349@4087 370 * depend on.
cl349@4087 371 *
cl349@4087 372 * No data-dependent reads from memory-like regions are ever reordered
cl349@4087 373 * over this barrier. All reads preceding this primitive are guaranteed
cl349@4087 374 * to access memory (but not necessarily other CPUs' caches) before any
cl349@4087 375 * reads following this primitive that depend on the data return by
cl349@4087 376 * any of the preceding reads. This primitive is much lighter weight than
cl349@4087 377 * rmb() on most CPUs, and is never heavier weight than is
cl349@4087 378 * rmb().
cl349@4087 379 *
cl349@4087 380 * These ordering constraints are respected by both the local CPU
cl349@4087 381 * and the compiler.
cl349@4087 382 *
cl349@4087 383 * Ordering is not guaranteed by anything other than these primitives,
cl349@4087 384 * not even by data dependencies. See the documentation for
cl349@4087 385 * memory_barrier() for examples and URLs to more information.
cl349@4087 386 *
cl349@4087 387 * For example, the following code would force ordering (the initial
cl349@4087 388 * value of "a" is zero, "b" is one, and "p" is "&a"):
cl349@4087 389 *
cl349@4087 390 * <programlisting>
cl349@4087 391 * CPU 0 CPU 1
cl349@4087 392 *
cl349@4087 393 * b = 2;
cl349@4087 394 * memory_barrier();
cl349@4087 395 * p = &b; q = p;
cl349@4087 396 * read_barrier_depends();
cl349@4087 397 * d = *q;
cl349@4087 398 * </programlisting>
cl349@4087 399 *
cl349@4087 400 * because the read of "*q" depends on the read of "p" and these
cl349@4087 401 * two reads are separated by a read_barrier_depends(). However,
cl349@4087 402 * the following code, with the same initial values for "a" and "b":
cl349@4087 403 *
cl349@4087 404 * <programlisting>
cl349@4087 405 * CPU 0 CPU 1
cl349@4087 406 *
cl349@4087 407 * a = 2;
cl349@4087 408 * memory_barrier();
cl349@4087 409 * b = 3; y = b;
cl349@4087 410 * read_barrier_depends();
cl349@4087 411 * x = a;
cl349@4087 412 * </programlisting>
cl349@4087 413 *
cl349@4087 414 * does not enforce ordering, since there is no data dependency between
cl349@4087 415 * the read of "a" and the read of "b". Therefore, on some CPUs, such
cl349@4087 416 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
cl349@4087 417 * in cases like thiswhere there are no data dependencies.
cl349@4087 418 **/
cl349@4087 419
cl349@4087 420 #define read_barrier_depends() do { } while(0)
cl349@4087 421
cl349@4087 422 #ifdef CONFIG_X86_OOSTORE
cl349@4087 423 /* Actually there are no OOO store capable CPUs for now that do SSE,
cl349@4087 424 but make it already an possibility. */
cl349@4087 425 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
cl349@4087 426 #else
cl349@4087 427 #define wmb() __asm__ __volatile__ ("": : :"memory")
cl349@4087 428 #endif
cl349@4087 429
cl349@4087 430 #ifdef CONFIG_SMP
sos22@5466 431 #define smp_wmb() wmb()
sos22@5466 432 #if defined(CONFIG_SMP_ALTERNATIVES) && !defined(MODULE)
sos22@5466 433 #define smp_alt_mb(instr) \
sos22@5466 434 __asm__ __volatile__("6667:\nnop\nnop\nnop\nnop\nnop\nnop\n6668:\n" \
sos22@5466 435 ".section __smp_alternatives,\"a\"\n" \
sos22@5466 436 ".long 6667b\n" \
sos22@5466 437 ".long 6673f\n" \
sos22@5466 438 ".previous\n" \
sos22@5466 439 ".section __smp_replacements,\"a\"\n" \
sos22@5466 440 "6673:.byte 6668b-6667b\n" \
sos22@5466 441 ".byte 6670f-6669f\n" \
sos22@5466 442 ".byte 6671f-6670f\n" \
sos22@5466 443 ".byte 0\n" \
sos22@5466 444 ".byte %c0\n" \
sos22@5466 445 "6669:lock;addl $0,0(%%esp)\n" \
sos22@5466 446 "6670:" instr "\n" \
sos22@5466 447 "6671:\n" \
sos22@5466 448 ".previous\n" \
sos22@5466 449 : \
sos22@5466 450 : "i" (X86_FEATURE_XMM2) \
sos22@5466 451 : "memory")
sos22@5466 452 #define smp_rmb() smp_alt_mb("lfence")
sos22@5466 453 #define smp_mb() smp_alt_mb("mfence")
sos22@5466 454 #define set_mb(var, value) do { \
sos22@5466 455 unsigned long __set_mb_temp; \
sos22@5466 456 __asm__ __volatile__("6667:movl %1, %0\n6668:\n" \
sos22@5466 457 ".section __smp_alternatives,\"a\"\n" \
sos22@5466 458 ".long 6667b\n" \
sos22@5466 459 ".long 6673f\n" \
sos22@5466 460 ".previous\n" \
sos22@5466 461 ".section __smp_replacements,\"a\"\n" \
sos22@5466 462 "6673: .byte 6668b-6667b\n" \
sos22@5466 463 ".byte 6670f-6669f\n" \
sos22@5466 464 ".byte 0\n" \
sos22@5466 465 ".byte 6671f-6670f\n" \
sos22@5466 466 ".byte -1\n" \
sos22@5466 467 "6669: xchg %1, %0\n" \
sos22@5466 468 "6670:movl %1, %0\n" \
sos22@5466 469 "6671:\n" \
sos22@5466 470 ".previous\n" \
sos22@5466 471 : "=m" (var), "=r" (__set_mb_temp) \
sos22@5466 472 : "1" (value) \
sos22@5466 473 : "memory"); } while (0)
sos22@5466 474 #else
cl349@4087 475 #define smp_rmb() rmb()
sos22@5466 476 #define smp_mb() mb()
sos22@5466 477 #define set_mb(var, value) do { xchg(&var, value); } while (0)
sos22@5466 478 #endif
cl349@4087 479 #define smp_read_barrier_depends() read_barrier_depends()
cl349@4087 480 #else
cl349@4087 481 #define smp_mb() barrier()
cl349@4087 482 #define smp_rmb() barrier()
cl349@4087 483 #define smp_wmb() barrier()
cl349@4087 484 #define smp_read_barrier_depends() do { } while(0)
cl349@4087 485 #define set_mb(var, value) do { var = value; barrier(); } while (0)
cl349@4087 486 #endif
cl349@4087 487
cl349@4087 488 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
cl349@4087 489
cl349@4087 490 /* interrupt control.. */
cl349@4087 491
cl349@4087 492 /*
cl349@4087 493 * The use of 'barrier' in the following reflects their use as local-lock
cl349@4087 494 * operations. Reentrancy must be prevented (e.g., __cli()) /before/ following
cl349@4684 495 * critical operations are executed. All critical operations must complete
cl349@4087 496 * /before/ reentrancy is permitted (e.g., __sti()). Alpha architecture also
cl349@4087 497 * includes these barriers, for example.
cl349@4087 498 */
cl349@4087 499
cl349@4087 500 #define __cli() \
cl349@4087 501 do { \
cl349@4112 502 vcpu_info_t *_vcpu; \
cl349@4112 503 preempt_disable(); \
cl349@4112 504 _vcpu = &HYPERVISOR_shared_info->vcpu_data[smp_processor_id()]; \
cl349@4112 505 _vcpu->evtchn_upcall_mask = 1; \
cl349@4112 506 preempt_enable_no_resched(); \
cl349@4087 507 barrier(); \
cl349@4087 508 } while (0)
cl349@4087 509
cl349@4087 510 #define __sti() \
cl349@4087 511 do { \
cl349@4112 512 vcpu_info_t *_vcpu; \
cl349@4087 513 barrier(); \
cl349@4112 514 preempt_disable(); \
cl349@4112 515 _vcpu = &HYPERVISOR_shared_info->vcpu_data[smp_processor_id()]; \
cl349@4112 516 _vcpu->evtchn_upcall_mask = 0; \
cl349@4087 517 barrier(); /* unmask then check (avoid races) */ \
cl349@4112 518 if ( unlikely(_vcpu->evtchn_upcall_pending) ) \
cl349@4112 519 force_evtchn_callback(); \
cl349@4112 520 preempt_enable(); \
cl349@4087 521 } while (0)
cl349@4087 522
cl349@4087 523 #define __save_flags(x) \
cl349@4087 524 do { \
cl349@4112 525 vcpu_info_t *_vcpu; \
cl349@4112 526 _vcpu = &HYPERVISOR_shared_info->vcpu_data[smp_processor_id()]; \
cl349@4112 527 (x) = _vcpu->evtchn_upcall_mask; \
cl349@4087 528 } while (0)
cl349@4087 529
cl349@4087 530 #define __restore_flags(x) \
cl349@4087 531 do { \
cl349@4112 532 vcpu_info_t *_vcpu; \
cl349@4087 533 barrier(); \
cl349@4112 534 preempt_disable(); \
cl349@4112 535 _vcpu = &HYPERVISOR_shared_info->vcpu_data[smp_processor_id()]; \
cl349@4112 536 if ((_vcpu->evtchn_upcall_mask = (x)) == 0) { \
cl349@4112 537 barrier(); /* unmask then check (avoid races) */ \
cl349@4112 538 if ( unlikely(_vcpu->evtchn_upcall_pending) ) \
cl349@4112 539 force_evtchn_callback(); \
cl349@4112 540 preempt_enable(); \
cl349@4112 541 } else \
cl349@4112 542 preempt_enable_no_resched(); \
cl349@4087 543 } while (0)
cl349@4087 544
cl349@4112 545 #define safe_halt() ((void)0)
cl349@4087 546
cl349@4087 547 #define __save_and_cli(x) \
cl349@4087 548 do { \
cl349@4112 549 vcpu_info_t *_vcpu; \
cl349@4112 550 preempt_disable(); \
cl349@4112 551 _vcpu = &HYPERVISOR_shared_info->vcpu_data[smp_processor_id()]; \
cl349@4112 552 (x) = _vcpu->evtchn_upcall_mask; \
cl349@4112 553 _vcpu->evtchn_upcall_mask = 1; \
cl349@4112 554 preempt_enable_no_resched(); \
cl349@4087 555 barrier(); \
cl349@4087 556 } while (0)
cl349@4087 557
cl349@4087 558 #define local_irq_save(x) __save_and_cli(x)
cl349@4087 559 #define local_irq_restore(x) __restore_flags(x)
cl349@4087 560 #define local_save_flags(x) __save_flags(x)
cl349@4087 561 #define local_irq_disable() __cli()
cl349@4087 562 #define local_irq_enable() __sti()
cl349@4087 563
kaf24@6551 564 /* Don't use smp_processor_id: this is called in debug versions of that fn. */
kaf24@6552 565 #ifdef CONFIG_SMP
cl349@4112 566 #define irqs_disabled() \
kaf24@6551 567 HYPERVISOR_shared_info->vcpu_data[__smp_processor_id()].evtchn_upcall_mask
kaf24@6552 568 #else
kaf24@6552 569 #define irqs_disabled() \
kaf24@6552 570 HYPERVISOR_shared_info->vcpu_data[0].evtchn_upcall_mask
kaf24@6552 571 #endif
cl349@4087 572
cl349@4087 573 /*
cl349@4087 574 * disable hlt during certain critical i/o operations
cl349@4087 575 */
cl349@4087 576 #define HAVE_DISABLE_HLT
cl349@4087 577 void disable_hlt(void);
cl349@4087 578 void enable_hlt(void);
cl349@4087 579
cl349@4087 580 extern int es7000_plat;
cl349@4087 581 void cpu_idle_wait(void);
cl349@4087 582
vh249@5730 583 extern unsigned long arch_align_stack(unsigned long sp);
vh249@5730 584
cl349@4087 585 #endif