xen-vtx-unstable

view xen/arch/x86/i8259.c @ 6759:b5d91089e42c

Newer binutils is a bit stricter and errors out when you try
to use movl on a 16 bit word on x86_64. Using just a "mov"
compiles fine and should result in the same code.

{standard input}: Assembler messages:
{standard input}:2138: Error: suffix or operands invalid for `mov'
{standard input}:2140: Error: suffix or operands invalid for `mov'
{standard input}:2142: Error: suffix or operands invalid for `mov'
{standard input}:2144: Error: suffix or operands invalid for `mov'

Signed-off-by: Rik van Riel <riel@redhat.com>
author kaf24@firebug.cl.cam.ac.uk
date Tue Sep 13 10:21:22 2005 +0000 (2005-09-13)
parents dd668f7527cb
children
line source
1 /******************************************************************************
2 * i8259.c
3 *
4 * Well, this is required for SMP systems as well, as it build interrupt
5 * tables for IO APICS as well as uniprocessor 8259-alikes.
6 */
8 #include <xen/config.h>
9 #include <xen/init.h>
10 #include <xen/types.h>
11 #include <asm/regs.h>
12 #include <xen/errno.h>
13 #include <xen/sched.h>
14 #include <xen/irq.h>
15 #include <asm/atomic.h>
16 #include <asm/system.h>
17 #include <asm/io.h>
18 #include <asm/desc.h>
19 #include <asm/bitops.h>
20 #include <xen/delay.h>
21 #include <asm/apic.h>
22 #include <io_ports.h>
24 /*
25 * Common place to define all x86 IRQ vectors
26 *
27 * This builds up the IRQ handler stubs using some ugly macros in irq.h
28 *
29 * These macros create the low-level assembly IRQ routines that save
30 * register context and call do_IRQ(). do_IRQ() then does all the
31 * operations that are needed to keep the AT (or SMP IOAPIC)
32 * interrupt-controller happy.
33 */
35 BUILD_COMMON_IRQ()
37 #define BI(x,y) \
38 BUILD_IRQ(x##y)
40 #define BUILD_16_IRQS(x) \
41 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
42 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
43 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
44 BI(x,c) BI(x,d) BI(x,e) BI(x,f)
46 BUILD_16_IRQS(0x0) BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
47 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
48 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
49 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
51 #undef BUILD_16_IRQS
52 #undef BI
55 /*
56 * The following vectors are part of the Linux architecture, there
57 * is no hardware IRQ pin equivalent for them, they are triggered
58 * through the ICC by us (IPIs)
59 */
60 BUILD_SMP_INTERRUPT(event_check_interrupt,EVENT_CHECK_VECTOR)
61 BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
62 BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
64 /*
65 * Every pentium local APIC has two 'local interrupts', with a
66 * soft-definable vector attached to both interrupts, one of
67 * which is a timer interrupt, the other one is error counter
68 * overflow. Linux uses the local APIC timer interrupt to get
69 * a much simpler SMP time architecture:
70 */
71 BUILD_SMP_TIMER_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
72 BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
73 BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
75 #define IRQ(x,y) \
76 IRQ##x##y##_interrupt
78 #define IRQLIST_16(x) \
79 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
80 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
81 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
82 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
84 static void (*interrupt[])(void) = {
85 IRQLIST_16(0x0), IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
86 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
87 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
88 IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
89 };
91 #undef IRQ
92 #undef IRQLIST_16
94 /*
95 * This is the 'legacy' 8259A Programmable Interrupt Controller,
96 * present in the majority of PC/AT boxes.
97 * plus some generic x86 specific things if generic specifics makes
98 * any sense at all.
99 * this file should become arch/i386/kernel/irq.c when the old irq.c
100 * moves to arch independent land
101 */
103 spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
105 static void disable_8259A_vector(unsigned int vector)
106 {
107 disable_8259A_irq(LEGACY_IRQ_FROM_VECTOR(vector));
108 }
110 static void enable_8259A_vector(unsigned int vector)
111 {
112 enable_8259A_irq(LEGACY_IRQ_FROM_VECTOR(vector));
113 }
115 static void mask_and_ack_8259A_vector(unsigned int);
117 static void end_8259A_vector(unsigned int vector)
118 {
119 if (!(irq_desc[vector].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
120 enable_8259A_vector(vector);
121 }
123 static unsigned int startup_8259A_vector(unsigned int vector)
124 {
125 enable_8259A_vector(vector);
126 return 0; /* never anything pending */
127 }
129 static struct hw_interrupt_type i8259A_irq_type = {
130 .typename = "XT-PIC",
131 .startup = startup_8259A_vector,
132 .shutdown = disable_8259A_vector,
133 .enable = enable_8259A_vector,
134 .disable = disable_8259A_vector,
135 .ack = mask_and_ack_8259A_vector,
136 .end = end_8259A_vector
137 };
139 /*
140 * 8259A PIC functions to handle ISA devices:
141 */
143 /*
144 * This contains the irq mask for both 8259A irq controllers,
145 */
146 static unsigned int cached_irq_mask = 0xffff;
148 #define __byte(x,y) (((unsigned char *)&(y))[x])
149 #define cached_21 (__byte(0,cached_irq_mask))
150 #define cached_A1 (__byte(1,cached_irq_mask))
152 /*
153 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
154 * boards the timer interrupt is not really connected to any IO-APIC pin,
155 * it's fed to the master 8259A's IR0 line only.
156 *
157 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
158 * this 'mixed mode' IRQ handling costs nothing because it's only used
159 * at IRQ setup time.
160 */
161 unsigned long io_apic_irqs;
163 void disable_8259A_irq(unsigned int irq)
164 {
165 unsigned int mask = 1 << irq;
166 unsigned long flags;
168 spin_lock_irqsave(&i8259A_lock, flags);
169 cached_irq_mask |= mask;
170 if (irq & 8)
171 outb(cached_A1,0xA1);
172 else
173 outb(cached_21,0x21);
174 spin_unlock_irqrestore(&i8259A_lock, flags);
175 }
177 void enable_8259A_irq(unsigned int irq)
178 {
179 unsigned int mask = ~(1 << irq);
180 unsigned long flags;
182 spin_lock_irqsave(&i8259A_lock, flags);
183 cached_irq_mask &= mask;
184 if (irq & 8)
185 outb(cached_A1,0xA1);
186 else
187 outb(cached_21,0x21);
188 spin_unlock_irqrestore(&i8259A_lock, flags);
189 }
191 int i8259A_irq_pending(unsigned int irq)
192 {
193 unsigned int mask = 1<<irq;
194 unsigned long flags;
195 int ret;
197 spin_lock_irqsave(&i8259A_lock, flags);
198 if (irq < 8)
199 ret = inb(0x20) & mask;
200 else
201 ret = inb(0xA0) & (mask >> 8);
202 spin_unlock_irqrestore(&i8259A_lock, flags);
204 return ret;
205 }
207 /*
208 * This function assumes to be called rarely. Switching between
209 * 8259A registers is slow.
210 * This has to be protected by the irq controller spinlock
211 * before being called.
212 */
213 static inline int i8259A_irq_real(unsigned int irq)
214 {
215 int value;
216 int irqmask = 1<<irq;
218 if (irq < 8) {
219 outb(0x0B,0x20); /* ISR register */
220 value = inb(0x20) & irqmask;
221 outb(0x0A,0x20); /* back to the IRR register */
222 return value;
223 }
224 outb(0x0B,0xA0); /* ISR register */
225 value = inb(0xA0) & (irqmask >> 8);
226 outb(0x0A,0xA0); /* back to the IRR register */
227 return value;
228 }
230 /*
231 * Careful! The 8259A is a fragile beast, it pretty
232 * much _has_ to be done exactly like this (mask it
233 * first, _then_ send the EOI, and the order of EOI
234 * to the two 8259s is important!
235 */
236 static void mask_and_ack_8259A_vector(unsigned int vector)
237 {
238 unsigned int irq = LEGACY_IRQ_FROM_VECTOR(vector);
239 unsigned int irqmask = 1 << irq;
240 unsigned long flags;
242 spin_lock_irqsave(&i8259A_lock, flags);
243 /*
244 * Lightweight spurious IRQ detection. We do not want
245 * to overdo spurious IRQ handling - it's usually a sign
246 * of hardware problems, so we only do the checks we can
247 * do without slowing down good hardware unnecesserily.
248 *
249 * Note that IRQ7 and IRQ15 (the two spurious IRQs
250 * usually resulting from the 8259A-1|2 PICs) occur
251 * even if the IRQ is masked in the 8259A. Thus we
252 * can check spurious 8259A IRQs without doing the
253 * quite slow i8259A_irq_real() call for every IRQ.
254 * This does not cover 100% of spurious interrupts,
255 * but should be enough to warn the user that there
256 * is something bad going on ...
257 */
258 if (cached_irq_mask & irqmask)
259 goto spurious_8259A_irq;
260 cached_irq_mask |= irqmask;
262 handle_real_irq:
263 if (irq & 8) {
264 inb(0xA1); /* DUMMY - (do we need this?) */
265 outb(cached_A1,0xA1);
266 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
267 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
268 } else {
269 inb(0x21); /* DUMMY - (do we need this?) */
270 outb(cached_21,0x21);
271 outb(0x60+irq,0x20); /* 'Specific EOI' to master */
272 }
273 spin_unlock_irqrestore(&i8259A_lock, flags);
274 return;
276 spurious_8259A_irq:
277 /*
278 * this is the slow path - should happen rarely.
279 */
280 if (i8259A_irq_real(irq))
281 /*
282 * oops, the IRQ _is_ in service according to the
283 * 8259A - not spurious, go handle it.
284 */
285 goto handle_real_irq;
287 {
288 static int spurious_irq_mask;
289 /*
290 * At this point we can be sure the IRQ is spurious,
291 * lets ACK and report it. [once per IRQ]
292 */
293 if (!(spurious_irq_mask & irqmask)) {
294 printk("spurious 8259A interrupt: IRQ%d.\n", irq);
295 spurious_irq_mask |= irqmask;
296 }
297 atomic_inc(&irq_err_count);
298 /*
299 * Theoretically we do not have to handle this IRQ,
300 * but in Linux this does not cause problems and is
301 * simpler for us.
302 */
303 goto handle_real_irq;
304 }
305 }
307 void __init init_8259A(int auto_eoi)
308 {
309 unsigned long flags;
311 spin_lock_irqsave(&i8259A_lock, flags);
313 outb(0xff, 0x21); /* mask all of 8259A-1 */
314 outb(0xff, 0xA1); /* mask all of 8259A-2 */
316 /*
317 * outb_p - this has to work on a wide range of PC hardware.
318 */
319 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
320 outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
321 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
322 if (auto_eoi)
323 outb_p(0x03, 0x21); /* master does Auto EOI */
324 else
325 outb_p(0x01, 0x21); /* master expects normal EOI */
327 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
328 outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
329 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
330 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
331 is to be investigated) */
333 if (auto_eoi)
334 /*
335 * in AEOI mode we just have to mask the interrupt
336 * when acking.
337 */
338 i8259A_irq_type.ack = disable_8259A_vector;
339 else
340 i8259A_irq_type.ack = mask_and_ack_8259A_vector;
342 udelay(100); /* wait for 8259A to initialize */
344 outb(cached_21, 0x21); /* restore master IRQ mask */
345 outb(cached_A1, 0xA1); /* restore slave IRQ mask */
347 spin_unlock_irqrestore(&i8259A_lock, flags);
348 }
350 static struct irqaction cascade = { no_action, "cascade", NULL};
352 void __init init_IRQ(void)
353 {
354 int i;
356 init_bsp_APIC();
358 init_8259A(0);
360 for ( i = 0; i < NR_IRQS; i++ )
361 {
362 irq_desc[i].status = IRQ_DISABLED;
363 irq_desc[i].handler = &no_irq_type;
364 irq_desc[i].action = NULL;
365 irq_desc[i].depth = 1;
366 spin_lock_init(&irq_desc[i].lock);
367 set_intr_gate(i, interrupt[i]);
368 }
370 for ( i = 0; i < 16; i++ )
371 {
372 vector_irq[LEGACY_VECTOR(i)] = i;
373 irq_desc[LEGACY_VECTOR(i)].handler = &i8259A_irq_type;
374 }
376 /*
377 * IRQ0 must be given a fixed assignment and initialized,
378 * because it's used before the IO-APIC is set up.
379 */
380 irq_vector[0] = FIRST_DEVICE_VECTOR;
381 vector_irq[FIRST_DEVICE_VECTOR] = 0;
383 /* Various IPI functions. */
384 set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
385 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
386 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
388 /* Self-generated IPI for local APIC timer. */
389 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
391 /* IPI vectors for APIC spurious and error interrupts. */
392 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
393 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
395 /* Set the clock to HZ Hz */
396 #define CLOCK_TICK_RATE 1193180 /* crystal freq (Hz) */
397 #define LATCH (((CLOCK_TICK_RATE)+(HZ/2))/HZ)
398 outb_p(0x34, PIT_MODE); /* binary, mode 2, LSB/MSB, ch 0 */
399 outb_p(LATCH & 0xff, PIT_CH0); /* LSB */
400 outb(LATCH >> 8, PIT_CH0); /* MSB */
402 setup_irq(2, &cascade);
403 }